Memory systems are used in a variety of applications where there is a need to store and access digital data, such as a computer system. During operation, memory systems occasionally fail to provide the data as stored. As a result, an error occurs. A memory system failing to provide correct data can be caused by several reasons. For example, the memory system is being operated under conditions that violate published specifications, the memory system has either a manufacture or design defects that escaped screening by final testing by the manufacturer, or the memory system is a random failure that escaped reliability and “burn-in” testing. When a memory system fails in the field, the manufacturer performs failure analysis on the memory system to determine the cause, or failure mode, of the failure. The manufacturer can then decide what corrective measures need to be taken to resolve the failures. This includes changing operating specifications for the memory system, implementing additional tests to screen out those memory systems most likely to fail under similar system operating conditions, and if necessary, modifying the design of the memory system.
As part of the failure analysis, a test algorithm or program simulating the memory system operating conditions causing the failure is developed so that the failures can be repeated in a controlled environment. The test program is typically developed for automated test equipment (ATE) designed for testing memory systems. Many such ATEs are available from companies, including Advantest, Schlumberger, Agilent, Credence, and several others. Current ATEs have the capability to perform testing by executing a test program having algorithmic test patterns, vector test patterns, or both. Generally, algorithmic test patterns are written as algorithms executed on test pattern generators in an ATE that exercise the memory system during testing. In contrast, vector test patterns are written as a series of commands, or test vectors, for the ATE that specify which signals and the logic states of those signals are to be applied to the memory system under test. As the series of test vectors are executed by the ATE, the memory system under test is exercised.
FIG. 1 is a block diagram illustrating various tools that are utilized during failure analysis of a memory system 102 that is included in a processing system 103. The memory system 102 represents various types of memory systems, including individual memory devices, memory modules, and systems having a plurality of memory devices or memory modules. In the present example, the memory system 102 is experiencing failures when operating in the processing system 103. Operation of the tools shown in FIG. 1 will be explained with reference to FIG. 2, which is a flow diagram illustrating the general process of developing a test program for an ATE 120 (FIG. 1) using the conventional analysis tools. The process begins at step 202 with sampling and recording the system operating conditions for the memory system 102 leading up to and including when a failure occurs in the memory system 102. Typically, a logic analyzer 104 or similar tool coupled to the memory system 102 is used to capture the logic states of various signals applied to the memory system 102 during operation in the processing system 103 at different clock cycles of a clock signal, which is also applied to the memory system 102. A record is created and stored for each point in time at which the logic states of the different signals applied to the memory system 102 are captured, and as the sampling at different points of time continues, a stored sequence of records is developed that provides a log of the system operating conditions resulting in the memory system failure.
The sequence of records generated by the logic analyzer 104 is converted into a textually formatted sequence of records 112, either directly by the logic analyzer 104, or as shown in FIG. 1, by a computer 108 that receives the sequence of records from the logic analyzer 104 and converts the sequence of records into the textually formatted sequence of records 112. At a step 204, the textually formatted sequence of records 112 is interpreted by an engineer whose task it is to develop a test program for the ATE 120 at a step 206 that can be used to confidently replicate failure of the memory system 102 in a controlled test environment. Where a test program having algorithmic test patterns is developed by the engineer, the algorithmic test patterns are loaded into a algorithmic test memory 130 for execution by the ATE 120. The ATE 120 further includes a vector test memory 140 for storing vector test patterns included in the test program which are executed on the ATE 120.
The test program is executed by the ATE 120 to test a memory system under test 124, which can represent the failing memory system 102, as well as memory systems that are the same as the memory system 102. The test program is used as part of the failure analysis process of determining the specific failure mode of the memory system 102 since understanding the specific operating conditions under which the memory system 102 fails can often provide valuable insight to the actual failure mode. As previously discussed, a test program developed by the engineer can be included in a production level test to screen out memory systems likely to experience the same failures as the memory system 102. Typically, production level tests primarily include algorithmic test patterns due to size constraints of the vector test memory 140 of the ATE 120, as well as the greater speed at which algorithmic test patterns can be executed by the ATE 120.
The process of developing a suitable test program from the textually formatted sequence of records 112 is resource intensive, often requiring many hours to review the sequence of records and develop a test program for the ATE 120 to reliably repeat the memory system failure. The system operating conditions causing a memory system failure can span thousands, if not millions of clock cycles. As a result, the textually formatted sequence of records 112 can be quite large, including considerable extraneous information unrelated to the specific cause of the failure. However, if the number of records of a sequence is reduced, the resulting textually formatted sequence of records 112 may have a sample resolution that fails to provide an adequately detailed history of the system operating conditions leading up to the failure to be used in developing a test program. Additionally, when a suspicious set of system operating conditions is identified from the sequence of records, manually developing a test program for the ATE 120 can be tedious and error-prone. Therefore, there is a need for an alternative system and method that facilitates analyzing failures of a memory system and developing a test program for an ATE that replicates the operating condition causing the memory system to fail.